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What are major UPS circuits ?
In addition to the rectifier circuit and inverter circuit mentioned above, the major UPS circuits also includes power factor correction circuit, transfer switch, protection circuit, auxiliary power supply and battery charging circuit. This chapter focuses on power factor correction circuit, transfer switch, protection circuit and auxiliary power supply, battery charging circuit will be detailed in the next chapter.
Power factor correction circuit
In electrician principle, the power factor PF (power factor) of linear circuit is conventionally defined as cosφ, φ is the phase Angle difference between sinusoidal voltage and sinusoidal current. However, due to the nonlinearity of rectifier devices and the storage of capacitor, the current distortion will occur even if the input voltage is sinusoidal. At this point, the power factor is defined as:
PF= Active power/apparent power
In the above formula, the active power is usually equal to the average instantaneous power, and power is defined as the product of voltage effective value and current effective value.
In the rectifier circuit, the secondary effect of harmonic current is omitted, and the input voltage can be regarded as sine and the input current as non-sine, where the effective value of the current is:
Where, Irms (n) is the effective value of the NTH harmonic.
Let the Angle by which the fundamental current lags behind the input voltage be 0, then PF of the circuit is
Where, Kd=Irms (L) /Irms, Kd is called current waveform distortion factor; Kθ=cosθ, Kθ is called phase shift factor, that is, the power factor is the product of current waveform distortion factor and phase shift factor.
Total spectral wave distortion (THD) is defined as
The relation between current waveform distortion factor Kd and THD is as follows
Power factor correction method
There are two kinds of power factor correction methods: passive power factor correction and active power factor correction.
Passive power factor correction circuit is the use of inductors and capacitors and other components of the filter, the input current waveform phase shift and shaping, using this method can make the power factor increased to more than 0.9, its advantages are simple circuit, low cost; The disadvantage is that the circuit is large in size and may cause resonance at certain frequency points and damage electrical equipment. Passive power factor correction circuits are mainly suitable for low power applications.
The active power factor correction circuit is to add a DC/DC switching converter between the rectifier and the filter capacitor. Its main idea is as follows: choose the input voltage of a reference signal, the input current tracking reference signal, the low frequency component of the input current and input voltage of an approximation of the same frequency and phase of the waveform, in order to improve the power factor and harmonic, USES the voltage feedback at the same time, make the output voltage of the approximate smooth dc output voltage.
The main advantages of active power factor correction are: high power factor can be obtained, such as 0.97~0.99, or even close to 1; Low total harmonic distortion (THD), can operate in a wide input voltage range (e.g., 90~264V, AC); Small size, light weight, output voltage is also maintained constant.
Passive power factor correction
There are two basic methods of passive power factor correction, that is, connecting a passive inductor L between a rectifier and a filter capacitor and using a capacitor and diode network to form a valley filled passive correction.
As shown in Figure 5-1 (a), the passive inductor L separates the rectifier from the dc capacitance C, so the voltage between the rectifier and the inductor L can change with the input voltage, and the conduction Angle of the rectifier diode increases, which improves the input current waveform.
The basic idea of valley filling passive correction is to use two series capacitors as filter capacitors, and to select several diodes, so that the two dc capacitors can be charged in series and discharged in parallel, so as to increase the diode conduction Angle and improve the input side power factor. Its circuit is shown in Figure 5-1 (b). Its basic principle is as follows: when the instantaneous input voltage rises to more than 1/2 peak value, that is, higher than the DC voltage on the DC filter capacitors Cd1 and Cd2, diode VD3 turns on, VD1 and VD2 cut off due to reverse bias, and the two DC filter capacitors Cd1 and Cd2 are in series charging state.
When the instantaneous input voltage decreases to below 1/2 peak value, that is, lower than the DC voltage on the DC filter capacitor Cd1 and Cd2, diode VD3 cuts off, VD1 and VD2 conduct, and the two DC filter capacitors Cd1 and Cd2 are in parallel discharge state. The critical point of dc filter capacitor Cd1 and Cd2 charging and discharging is at the 1/2 peak of the input voltage, arcsin (1/2) =30°, so theoretically the conduction Angle of rectifier diode is not less than 180°-30°2=120°, which is significantly higher than that when a DC filter capacitor is used.
Active power factor correction
① Main circuit structure of active power factor correction.
The main circuit of active POWER factor correction circuit usually adopts DC/DC down converter, among which output Boost converter has the characteristic of continuous inductor current, and energy storage inductor can also be used as filter inductor to suppress EMI noise. In addition, it also has the advantages of small current distortion, large output power and simple driving circuit, so it is widely used. In addition to the Boost output converter, buck-Boost, Flyback and Cuk converters can be used as the main circuit of active power correction.
② Control method of active power factor correction.
The idea of active power factor correction technology is to control the current after rectification, so that it can be the same as the voltage waveform after rectification before charging the filter capacitor, so as to avoid the formation of current pulse, and achieve the purpose of improving the power factor. Figure 5-2 shows the principle of the active POWER factor correction circuit. The main circuit is a full-wave rectifier, which implements AC/DC conversion without distortion of voltage waveform.
Before the filter capacitor C is a Boost converter to implement the Boost type DC/DC conversion. From the point of view of the control loop, it consists of a voltage outer ring and a current inner ring. During the operation, the current in the booster inductor L1 is continuously monitored and adjusted to follow the sinusoidal half-wave voltage waveform after rectification.
The output voltage uD of the rectifier and the difference between the output capacitance voltage uC of the boost converter and the given voltage Uc * serve as the input of the multiplier to form the voltage outer ring, and the output of the multiplier Is the given current of the current ring Is*.
The purpose of comparing the output capacitor voltage uCof the boost converter with the given voltage Uc * is to judge whether the output voltage is the same as the given voltage. If not, the regulator can adjust it to be the same as the given voltage. The output of the regulator (the operational amplifier in the figure) is a DC value, which is the role of the voltage loop. The output voltage ud of the rectifier is obviously a sinusoidal half-wave voltage waveform, which is unchanged when multiplied by the result of the regulator, so it is obviously also a sinusoidal half-wave waveform and is in phase with UD.
Taking the output of the multiplier as the given signal Is* of the current loop ensures that the controlled inductance current iL Is consistent with the voltage waveform UD. The amplitude of Is* Is related to the difference between the output voltage uC and the given voltage Uc * and also to the amplitude of UD. Current detection signals in L1 iF and Is* form a current loop to generate PWM signal, that Is, the driving signal of switch V. V conduction, inductance current increased iL. When iL Is increased to equal to the current Is*, V cuts off, the diode turns on, the power supply and L1 release energy, charging capacitor C and supplying power to the load at the same time, this Is the role of the current loop.
By a step-up (Boost) working principle of dc converter, the current in the Boost inductance L1 is continuous and discontinuous work mode, so you can get in the current loop PWM signals that switch V driver has produced two kinds of ways: one is inductive current critical continuous control mode, another is inductive current continuous control method. Figure 5-3 shows the voltage and current waveforms under the two control modes.
As shown in FIG. 5-3 (a), when switch V cutoff, the inductance current iL just drops to zero: when switch on, iL begins to rise gradually from zero; The peak iL Is exactly equal to the given current value Is*. That is, when the switch V is on, the inductance current rises from zero; When the switch shuts off, the inductance current drops from peak to zero. The peak envelope of inductance iL Is Is*.
Therefore, this current critical continuous control mode is also called peak current control mode. FIG. 5-3(b) Controlling the inductance current iL on the given current Is*curve, the high frequency broken line approximates the sinusoidal curve. Therefore, this Is current hysteresis control, Is* reflects the average current, so this continuous current control mode Is called average current control mode. After the inductance current iL is filtered by C1 and RF, the fundamental current II with the same coincidence rate as the input voltage is obtained.
At the same output power, the current capacity of the switch tube controlled by peak current is twice as large. Average current control, within the sine half-wave, inductor current is less than zero, before each DC/DC switch conduction, inductance L1 and diode VD are current, in the opening of the moment, so the switch the current and the diode reverse recovery in VD current in L1 to V DC conversion circuit of switching devices and the diode to form the “killer” life, Special care should be taken when selecting components. And the peak current control does not have this disadvantage, as long as the detection of the inductance current drop rate of change, when the current over zero will allow the switch to open, and the peak current with a current limiting resistance detection can reach the day, so cheap and reliable, suitable for small power occasions.
Typical power factor correction circuit
In the power supply system, the average current control mode is widely used, it has the advantages of good stability and small distortion, and its maximum application power can reach 6kW, the following introduces the typical controller UC3854 and its application.
UC3854 is a special control circuit for active power factor correction. It can complete all the control functions required by the power factor correction of the boost converter, making the power factor above 0.99 and the distortion of the input current waveform less than 5%. The controller adopts average current type control with high control precision and low switching noise.
After using UC3854 power factor correction circuit, not only can correct the power factor, but also can keep the output voltage stable (when the input voltage changes between 80 and 260V), so it can also be used as AC/DC voltage regulator. UC384 adopts push-pull output stage, its output current can reach more than 1A, so the output fixed PWM pulse can drive high power MOSFET.
Internal block diagram of UC3854 and its composition
Figure 5-4 shows the internal block diagram of the UC3854.
① Under-voltage blocking comparator (UVLC).
When the supply voltage Vcc is higher than 16V, the reference voltage is established, the oscillator starts oscillating, and the output stage outputs PWM pulses. When the supply voltage Vcc is below 10V, the reference voltage is interrupted, the oscillator stops oscillating, and the output stage is blocked.
② Enable the comparator (EC).
Enable pin (pin 10) output voltage is higher than 2.5V, output stage output driving pulse; When the output voltage of the enable pin is lower than 2.25V, the output stage is off.
The output of UVLC comparator and EC comparator is respectively connected to the input end of the gate. Only when both comparators output high voltage, can the reference voltage be established and the device output pulse.
③Voltage error amplifier (VEA).
The output voltage of the POWER factor correction circuit is applied to the reverse input of the voltage error amplifier (VEA) after passing through the resistor divider circuit. The difference between the output voltage and the 7.5V reference voltage is amplified and added to one of the input terminals of the multiplier (A).
④ Multiplier (MUL).
In addition to the error voltage, the multiplier input signal has current IAC (B terminal) and feed-forward voltage VRMS (C terminal) which are proportional to the rectified AC voltage.
⑤ Current error amplifier (CEA).
The reference current IMO output by the multiplier generates a reference voltage at both ends of the resistor RMO. After the voltage drop at both ends of the detection resistance RS and the voltage at both ends of RMO are subtracted, the current sampling signal is generated and added to the input end of the current error amplifier. The error signal is amplified by the current error amplifier (CEA) and then added to the input end of the PWM comparator to adjust the width of the output pulse by comparing with the sawtooth wave voltage of the oscillator.
⑥ Oscillator (OSC).
The oscillation frequency of the oscillator is determined by the external capacitance CT of pin 14 and the external resistance RSET of pin 12. The oscillator starts to oscillate only after the reference voltage is established.
⑦PWM comparator (PWMCOMP)
Current error amplifier (CEA) output signal and oscillator sawtooth wave voltage after comparison, generate pulse width modulation signal, the signal is added to the trigger (FIIPFLOP).
⑧Flip-flop, oscillator (OSC) and PWM comparator (PWMCOMP)
Output signal respectively added to FLIP FLOP R, S end, control the output pulse of the trigger, the pulse after the gate circuit and push and pull output stage, drive the external power MOSFET.
⑨ Reference power supply (REF).
The reference voltage REF is controlled by the undervoltage blocking comparator (UVLC) and enable comparator (EC). Pin 9 can output 7.5V reference voltage when both comparators output high voltages.
⑩ Peak current limit comparator (LMT).
The current sampling signal is added to the input end of the comparator. When the output current reaches a certain value, the comparator shuts off the output pulse through a trigger.
⑪The soft start circuit (SS).
After the reference voltage is established, 14μA current is applied to the external capacitor CSS of pin SS (pin 13). At the beginning of charging, the voltage of pin 13 is zero, the isolation diode connected in pin 13 is turned on, the reference voltage of the voltage error amplifier (VEA) is zero, and the UC3854 has no output pulse. When theCSS is fully charged, the isolation diode is turned off, the soft-start capacitor is isolated from the voltage error amplifier, and the soft-start process is complete.
The UC3854 normally outputs pulses. When undervoltage blockade or enable shutdown occurs, the output signal of the door not only shuts off the output, but also enables the internal transistors at both ends of the CSS to conduct, so as to discharge the CSS to ensure that the CSS is charged from zero at the next startup.
Pin arrangement and function
The UC3854 can be packaged in a variety of formats, such as DIL-16, SOIC-16, PLCC-20, and LCC-20. However, DliL1 is commonly used. Figure 5-5 shows the pin arrangement in this format.
①GND (pin 1) Ground terminal: test reference point for all voltages. The discharge current of the oscillator’s timing capacitor is also returned by this pin. Therefore, the timing capacitor to the pin distance should be as short as possible.
② (pin 2) peak current limiting end: peak current limiting threshold is 0V, the pin should be connected to the negative voltage of the current sampling resistance. A resistor should be connected between this pin and reference voltage pin VREF (pin 9) in order for the current sampling voltage to rise to ground potential.
③ CA Out (pin 3) current amplifier input: the pin is the output of the voltage error amplifier, which detects and amplifies the power grid input current, controls the pulse width modulator, and forces the correction of the power grid input current.
④ ISENSE (pin 4) Current sampling voltage negative: the pin is the current amplifier inverting end.
⑤ Mult Out (pin 5) Output end of analog multiplier and positive pole of current sampling voltage: output of analog multiplier is directly connected to the in-phase input end of current amplifier.
⑥IAC (pin 6) Input AC current sampling signal: THE IAC is added to the analog multiplier from the pin.
⑦VA Out (pin 7) voltage amplifier output: the pin voltage can adjust the output voltage.
VRMS (pin 8) RMS voltage input end: rectifier bridge output voltage partial pressure added to the pin, in order to achieve the best control, the pin voltage should be between 1.5~3.5V.
⑨VREF (pin 9) Reference voltage output terminal: this pin outputs a reference voltage of 7.5V with a maximum output current of 10mA and can be current limited internally. When THE VCC is low or the enable pin ENA is low, the pin voltage is zero and a capacitor with a capacity of 0.1μF should be connected to the ground.
⑩ENA (pin 10) Enable control: input of the logical control signal that outputs the PWM driving voltage of the UC3854. The signal also controls the reference voltage, oscillator and soft start circuit. When control is not required, the pin should be connected to a 5V power supply or to a VCC pin through a 100K ω resistor.
⑪The inverting input of the voltage amplifier (pin 11) : the output voltage of the power factor correction circuit is applied to this pin after voltage divider. An RC compensation network shall also be added between the pin and the output end of the voltage amplifier (pin 7).
⑫RSET (pin 12) oscillator timing capacitor charging current and access end of multiplier maximum output current setting resistor. A resistance is connected between the pin and the ground to set the charging current of the timing capacitor and the maximum output current of the multiplier. The maximum output current of the multiplier is 3.75V/RSET.
⑬SS (pin 13) soft start: when the UC3854 stops working or the VCC is too low, this pin voltage is zero. After starting to work, 14μA current external capacitor charge, the pin voltage gradually increased to 7.5V, PWM pulse duty ratio gradually increased, output voltage gradually increased.
⑭Timing capacitor access terminal: Timing capacitor CT is connected between the pin and ground, and the working frequency of the oscillator can be set by pressing the formula.
F = 1.25 / RSETCT
⑯ VCC (lead chest 15) positive power supply voltage; In order to ensure normal operation, the chest voltage should be higher than 17V. In order to absorb the current peak generated when the external MOSFET gate capacitor is charged, a bypass capacitor should be connected between the pin and the ground.
⑯Grid drive voltage output: This pin output voltage drives an external MOSFET power tube. The pin is internally connected with a clamping circuit, which can clamp the output pulse amplitude at 15. Therefore, when the device can still work normally. In practice, a pin greater than 5 ω should be connected to the gate of the MOSFET
Resistance, so as not to drive capacitance load, current overshoot phenomenon.
Actual application circuit
Figure 5-6 shows the 250W power factor correction circuit composed of the UC3854. The input voltage range of the circuit is 85~265V, and the power factor can reach more than 0.99.
The basic composition of the circuit. The circuit is based on UC3854 control circuit and boost converter circuit. The boost converter circuit is composed of 1mH boost inductor, power MOSFET (APT5052), isolation diode (UHV806) and 450μF filter capacitor. The boost inductor operates in a current continuous state. In this operating state, the pulse duty ratio is determined by the ratio of input voltage to output voltage, and the ripple of input current is very small, so the grid noise is relatively low. In addition, the output voltage of the boost converter must be higher than the peak output voltage of the grid.
The control circuit consists of UC3854 and its external components. Pin GT Drv output PWM pulse is added to the gate of the power leather MOSFET. The duty cycle of the pulse drive is simultaneously controlled by the following four input signals:
- Vsense(pin 11) : Direct input voltage sampling signal.
- IAC(pin 6) : grid voltage – shaped sampling signal.
- IENSE/Mult Out (pin 4/ Pin 5) : grid current sampling signal.
- VRMS(pin 8) : sampling signal of network voltage RMs.
② Design of protection input
Ena (enable) : Reference voltage and drive voltage (GT Drv) can be established only after the pin voltage reaches 2.5V. The drive signal can be output only after the power is switched on and after a certain delay. If this function is not used, the pin should be connected to the VCC pin through 100K ω resistance.
B.SS (soft start) : the pin voltage can lower the reference voltage of the voltage error amplifier in order to adjust the dc output voltage of the circuit under the power factor calibration. The pin can output 14μA current and charge the 0.01μF soft start capacitor to increase the voltage at both ends of the capacitor from 0V to 7.5V.
PECLMT (peak current limiting) : This pin input signal limits the maximum current of a power MOSFET. When the voltage at both ends of the 0.25 ω current sampling resistor is (7.sv2k ω)/10k ω =1.5V, the maximum current is 6A (6a0.25 ω =1.5V), the voltage of the pin PK LMT is 0V, and the output current is greater than 6A. The current limiting starts. To filter out high-frequency noise, a 470pF bypass capacitor should be connected between the pin and ground.
③ Design of control input
VSENSE(output DC voltage sampling) : VSENSE input threshold voltage is 7.5V, input bias current is 50 μA, the output piezoelectric resistance should ensure that the pin input voltage is not higher than 7.5V, for example:
The 180K ω resistor and 47nF capacitor in Figure 5-6 constitute the voltage amplifier compensation network.
IAC(power grid voltage waveform sampling signal) : the power grid voltage waveform sampling signal must be added to the pin IAC for the waveform of the forced power grid input current to be the same as that of the input voltage. The signal (IAC) is multiplied with the output signal of the voltage error amplifier in the multiplier to produce the reference current signal of the current control loop.
When the grid input voltage is over zero, the current of the pin IAC is zero, and when the grid input voltage reaches its peak, the current of the pin IAC should be 400μA, so RAC can be calculated as follows:
The RREF of resistance between lead IAC and reference voltage (UREF) lead should be:
- ISENSE/Mult Out (grid input current sampling) : The voltage drop at both ends of the 0.25 ω current sampling resistor is applied between pins 4 and 5 (the two inputs of the current amplifier). The 620pF and 24K ω resistor form the compensation network of the current amplifier. The current amplifier has a very wide bandwidth, so that the network current can be changed with the voltage.
- VRMS(sampling of network voltage RMS) : the ac input voltage of this circuit can vary between 85 and 260V. The network voltage RMS feedforward circuit is adopted to ensure that the input power is unchanged when the input voltage changes (assuming the load power is unchanged). For this reason, in the multiplier, the network current must be divided by the square of the network voltage RMS. The voltage applied to pin 8 (VRMS) is proportional to the average (and also proportional to the RMS) of the rectified grid voltage. The voltage is squared inside the chip as the divisor of the multiplier. The output current of the multiplier IMO (pin 5) is proportional to the voltage of the input current IAC of pin 6 and the voltage amplifier output of pin 7, and inversely proportional to the square of the VRMS voltage of pin 8, i.e
④ SETTING of PWM frequency. In this circuit, the oscillator operates at a frequency of 100kHz, which is determined by the external capacitance CT of pin 14 and the external resistance RSET of pin 12. When designing the circuit, the RSET should be determined first, because this resistance value affects the maximum output current IMULT (Max) of the multiplier:
When the RSET is 15K ω resistor
When a 4K ω resistor is connected between the output of the multiplier (pin 5) and the 0.25 ω sampling resistor, the maximum current in the current sampling resistor is:
After RSET is determined, the capacity of timing capacitor CT can be calculated according to the required switching frequency F.
